Regviz

Silicon Labs /EFR32BG24A010F1024IM48 /RAC_NS /AUXADCEN

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as AUXADCEN

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Silicon Labs/EFR32BG22C112F352GM32/RAC_S/AUXADCEN#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Disabled)AUXADCENAUXADC 0 (Disabled)AUXADCENINPUTBUFFER 0 (Disabled)AUXADCENLDO 0 (Disabled)AUXADCENOUTPUTDRV 0 (Disabled)AUXADCENPMON 0 (Disabled)AUXADCENRESONDIAGA 0 (Disabled)AUXADCENTSENSE 0 (Disabled)AUXADCENTSENSECAL 0 (Not_Bypassed)AUXADCINPUTBUFFERBYPASS 0 (Disabled)AUXADCENMEASTHERMISTOR

AUXADCENTSENSE=Disabled, AUXADCENLDO=Disabled, AUXADCINPUTBUFFERBYPASS=Not_Bypassed, AUXADCENAUXADC=Disabled, AUXADCENTSENSECAL=Disabled, AUXADCENMEASTHERMISTOR=Disabled, AUXADCENINPUTBUFFER=Disabled, AUXADCENRESONDIAGA=Disabled, AUXADCENOUTPUTDRV=Disabled, AUXADCENPMON=Disabled

Fields

AUXADCENAUXADC

AUXADCENAUXADC

0 (Disabled): undefined

1 (Enabled): undefined
AUXADCENINPUTBUFFER

AUXADCENINPUTBUFFER

0 (Disabled): undefined

1 (Enabled): undefined
AUXADCENLDO

AUXADCENLDO

0 (Disabled): undefined

1 (Enabled): undefined
AUXADCENOUTPUTDRV

AUXADCENOUTPUTDRV

0 (Disabled): undefined

1 (Enabled): undefined
AUXADCENPMON

AUXADCENPMON

0 (Disabled): undefined

1 (Enabled): undefined
AUXADCENRESONDIAGA

AUXADCENRESONDIAGA

0 (Disabled): undefined

1 (Enabled): undefined
AUXADCENTSENSE

AUXADCENTSENSE

0 (Disabled): undefined

1 (Enabled): undefined
AUXADCENTSENSECAL

AUXADCENTSENSECAL

0 (Disabled): undefined

1 (Enabled): undefined
AUXADCINPUTBUFFERBYPASS

AUXADCINPUTBUFFERBYPASS

0 (Not_Bypassed): undefined

1 (Bypassed): undefined
AUXADCENMEASTHERMISTOR

AUXADCENMEASTHERMISTOR

0 (Disabled): undefined

1 (Enabled): undefined

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data